(1) Field of the Invention
The present invention relates to a defective cell repairing circuit and method of a semiconductor memory device, and more particularly to a circuit and method capable of repairing a defective cell after the completion of the packaging process for the device.
(2) Description of the Related Art
Generally, semiconductor memory devices are designed to include a redundant cell to replace a defective cell occurring among normal cells, to improve the yield of a memory production process. Such devices are further designed to include a fuse and a redundant cell selecting circuit for fusably remapping the redundant cell to the address of the defective cell, so that the redundant cell is selected when the address of the defective cell is thereafter inputted from outside.
A conventional defective cell repairing circuit for performing the functions as described above is shown in FIG. 1, and disclosed in U.S. Pat. No. 4,473,895 issued to Tatematsu. In the operation of the circuit of FIG. 1, when an address is applied from the outside, it is compared with the stored defective cell address, thereby determining whether or not the redundant cell is selected. The defective cell address is stored by cutting a fuse 61 corresponding to the address lines for selecting the defective cell.
According to the conventional circuit in FIG. 1, in which the fuse 61 is used to store the defective cell address, the fuse cutting method is as follows. A high voltage is applied to a pad 63 and the address corresponding to the defective cell address is provided from the outside. Accordingly, a node of either the address Ai (i=0-8) or Ai goes to a logic "high" state, thereby turning ON an NMOS transistor 62 connected to the corresponding node. Thereby, a large amount of an electrical current due to the high voltage applied to pad 63 flows through the fuse 61, and each fuse 61 corresponding to the defective cell address is cut. At this time, one of the two fuses 61 connected to the two NMOS transistors 62 for each address pair Ai and Ai is inevitably cut. In other words, each bit of the defective cell address is stored according to which one of the two fuses 61 is cut.
After repairing the defective cell, when an address which does not correspond to the defective cell is provided from the outside, an NMOS transistor 64 is turned ON by a clock .phi.P when the semiconductor memory device is enabled, and then the node L is precharged to a power supply voltage level. Because the applied address does not correspond to the defective cell, at least one of the NMOS transistors 62 connected to an uncut fuse 61 is turned ON. The node L is discharged to a logic "low" state, thereby turning OFF an NMOS transistor 65. Thereafter, when a clock .phi.R is enabled, a node P is discharged to the logic "low" level. According to the conventional circuit, if the node P is the logic "low" state, a normal cell is selected.
Finally, after repairing the defective cell, when an address which corresponds to the defective cell is provided from the outside after the node L is precharged to the logic "high" state by the clock .phi.P, the inputted address is the same as the programmed address. Therefore, the NMOS transistors 62 connected to the fuses 61 that were previously cut are all turned OFF. Accordingly, since a discharging path is not formed by maintaining the node L in the logic "high" state, the NMOS transistor 65 maintaining the turned-ON state. As a result, though the NMOS transistor 65 is temporarily turned ON by the clock .phi.R, the node P maintains the logic "high" state. Accordingly, the redundant cell instead of the defective cell is selected.
In the conventional semiconductor memory device as mentioned above, in order to program the defective cell address, an electrical fuse cutting method or a fuse cutting method using a laser beam is used. In the case Of the laser beam cutting method, it is possible to repair the defective cell detected in a wafer state, but it is impossible to repair the defective cell detected in a package state. Likewise, in the case of the electrical fuse cutting method as shown in FIG. 1, if the additional pad 63 is required to apply fuse cutting power to the wafer, it becomes impossible to repair the defective cell after the packaging process.
As the integration of the semiconductor memory device increases, the number of memory cells and chip sizes accordingly increase, but the design rule decreases. Therefore, the possibility that a defective cell occurs is increased. Hence, if it is possible to repair a defective cell detected after the packaging process as well as in the wafer state, the production yield can be improved. Presently, a burn-in test is commonly used to detect defective cells and to ensure the reliability of the device. The burn-in test is normally performed on devices in the package state. Therefore, a novel device capable of repairing defective cells generated by a bum-in test performed after the package state is greatly needed.